CPU Exercises

Approach: Present the structure as four blocks — the ALU, the control unit, the register set, and the internal buses — each with its constituent parts, and then state the three functions the CPU performs over that structure.

Steps:

1. Arithmetic logic unit (ALU):
   • Arithmetic logic unit: performs arithmetic and logical operations
   • Accumulator: stores the result of an operation
   • General-purpose registers: store operands and intermediate results
   • Flag register: stores the status flags of the operation
2. Control unit:
   • Instruction register: stores the instruction currently being executed
   • Program counter: stores the address of the next instruction
   • Instruction decoder: analyses the meaning of the instruction
   • Timing controller: generates the control signals
3. Register set:
   • General-purpose registers: R0-R15, store data
   • Special-purpose registers: PC, SP, BP, and so on
   • Status register: stores the status information of the CPU
4. Internal buses:
   • Data bus: transfers data
   • Address bus: transfers addresses
   • Control bus: transfers control signals
5. The main functions:
   • Control function: controls the coordinated operation of all the components of the computer
   • Arithmetic function: performs arithmetic and logical operations
   • Coordination function: coordinates the work of memory and I/O devices

Answer: The basic structure of the CPU consists of the arithmetic logic unit (with its arithmetic logic unit, accumulator, general-purpose registers, and flag register), the control unit (with the instruction register, program counter, instruction decoder, and timing controller), the register set (general-purpose registers R0-R15, special-purpose registers such as PC, SP, and BP, and the status register), and the internal buses (data, address, and control). Its three main functions are the control function, which drives the coordinated operation of the whole machine, the arithmetic function, which performs the arithmetic and logical operations, and the coordination function, which coordinates memory and I/O devices and manages interrupts.

Approach: Walk through the cycle in order, naming the five stages and the concrete work each one performs, and then state the property that ties them together.

Steps:

1. Fetch stage (IF):
   • Fetches the instruction from memory
   • Updates the program counter
   • Moves the instruction into the instruction register
2. Decode stage (ID):
   • Analyses the operation code of the instruction
   • Determines the address of the operands
   • Prepares the resources needed for execution
3. Execute stage (EX):
   • Performs the arithmetic or logical operation
   • Computes the effective address
   • Performs the data transfer
4. Memory access stage (MEM):
   • Accesses the data memory
   • Reads or writes the data
   • Handles memory access conflicts
5. Write-back stage (WB):
   • Writes the result of the operation back into the register
   • Updates the status flags
   • Completes the execution of the instruction

Answer: The instruction execution process consists of five stages: fetch (IF), decode (ID), execute (EX), memory access (MEM), and write-back (WB). Together these five stages form the basic instruction cycle, although different types of instruction may skip some of them.

Approach: Answer in five layers — what the data path moves, how it supports instruction execution, how it improves performance, how it steers the data, and how it keeps the data consistent — so that the answer covers both the static structure and the dynamic behaviour.

Steps:

1. Realising data transfer:
   • Transfers data among the components inside the CPU
   • Connects the ALU, the registers, and memory
   • Supports different data widths and formats
2. Supporting instruction execution:
   • Provides the path along which an instruction executes
   • Realises the reading of the operands and the writing back of the result
   • Supports all the addressing modes
3. Optimising performance:
   • Raises the efficiency through parallel transfers
   • Reduces the data transfer latency
   • Supports pipelined operation
4. Controlling the flow of data:
   • Controls the source of the data through the multiplexers
   • Realises conditional transfers and branches
   • Supports the forwarding technique
5. Guaranteeing data consistency:
   • Ensures the reliability of data transfer
   • Handles data conflicts and races
   • Maintains data integrity

Answer: The data path is the route along which data flows inside the CPU. It realises the transfers among the ALU, the registers, and memory; it provides the path that instruction execution needs, covering the reading of operands, the writing back of results, and every addressing mode; it improves performance through parallel transfers, lower latency, and pipelined operation; it steers the data through the multiplexers to support conditional transfers, branches, and forwarding; and it guarantees consistency by handling data conflicts and maintaining integrity.

Approach: Compare the two designs on the seven axes that separate them — implementation, speed, flexibility, complexity, application scenario, debugging difficulty, and power consumption.

Steps:

1. Implementation:
   • Hardwired control unit: implemented with a combinational logic circuit
   • Microprogrammed control unit: implemented with a sequence of microinstructions
2. Speed:
   • Hardwired control unit: fast, with a small delay
   • Microprogrammed control unit: slower, because it has to access memory
3. Flexibility:
   • Hardwired control unit: inflexible and hard to modify
   • Microprogrammed control unit: highly flexible and easy to modify
4. Complexity:
   • Hardwired control unit: the hardware is complex and the design is difficult
   • Microprogrammed control unit: the hardware is comparatively simple
5. Application scenario:
   • Hardwired control unit: RISC processors, which pursue speed
   • Microprogrammed control unit: CISC processors, which pursue flexibility
6. Debugging difficulty:
   • Hardwired control unit: hard to debug, since the internal state is hard to observe
   • Microprogrammed control unit: comparatively easy to debug, since the microinstruction execution can be observed
7. Power consumption:
   • Hardwired control unit: comparatively high power consumption
   • Microprogrammed control unit: comparatively low power consumption

Answer: A hardwired control unit is built from combinational logic, so it is fast and has a small delay but is inflexible and hard to modify, its hardware is complex, it is hard to debug, and it consumes more power; it is used in RISC processors that chase speed. A microprogrammed control unit is built from a sequence of microinstructions, so it is slower because it has to access the control store, but it is highly flexible and easy to modify, its hardware is comparatively simple, debugging is easier because the microinstruction execution can be watched, and its power consumption is lower; it is used in CISC processors that chase flexibility.

Approach: Define the pipeline in three points, then list its advantages as a numbered set — throughput, CPU utilisation, performance, support for complex instructions, and ease of optimisation — each with the reason behind it.

Steps:

1. The definition of an instruction pipeline:
   • Decomposes the execution of an instruction into several stages
   • Different stages of different instructions can execute in parallel
   • Raises the throughput of the CPU
2. The advantages:
   1. Higher throughput:
      • Several instructions execute in parallel
      • In the ideal case the throughput equals the number of pipeline stages
      • Significantly improves CPU performance
   2. Higher CPU utilisation:
      • Reduces the idle time of the CPU
      • Makes full use of the hardware resources
      • Raises the overall efficiency
   3. Higher performance:
      • Improves performance at the same clock frequency
      • Reduces the average execution time per instruction
      • Raises the response speed of the system
   4. Support for complex instructions:
      • Decomposes complex instructions into simple stages
      • Makes complex functionality easy to implement
      • Keeps the hardware simple
   5. Ease of optimisation:
      • Each stage can be optimised independently
      • Supports a variety of optimisation techniques
      • Makes performance tuning convenient

Answer: An instruction pipeline decomposes the execution of an instruction into several stages, allows different stages of different instructions to execute in parallel, and thereby raises the throughput of the CPU. Its advantages are a higher throughput — in the ideal case equal to the number of stages — a higher CPU utilisation because idle time is reduced and the hardware is fully used, higher performance at the same clock frequency since the average execution time per instruction falls, the ability to implement complex instructions by decomposing them into simple stages while keeping the hardware simple, and ease of optimisation, since each stage can be tuned independently.

Approach: Take the three hazards in turn, describing for each what causes it, what it costs, and how it is solved, then aggregate the effect on CPI and throughput, and close with the optimisation strategy at the hardware, software, and system level.

Steps:

1. Data hazard:
   • Impact: a later instruction needs the result of an earlier instruction
   • Performance loss: the pipeline has to be stalled or the result forwarded
   • Solutions: data forwarding, register renaming, pipeline stalls
2. Control hazard:
   • Impact: a branch instruction changes the order of execution
   • Performance loss: the pipeline has to be flushed, losing several clock cycles
   • Solutions: branch prediction, delayed slots, speculative execution
3. Structural hazard:
   • Impact: several instructions need the same hardware resource
   • Performance loss: the conflicting instruction has to be stalled
   • Solutions: adding hardware resources, pipeline stalls, resource scheduling
4. Overall impact:
   • CPI increase: the actual CPI > 1
   • Throughput decrease: the ideal throughput cannot be reached
   • Performance loss: possibly a loss of 20-40% of the performance
5. Optimisation strategy:
   • Hardware optimisation: add resources, improve the prediction
   • Software optimisation: compiler optimisation, instruction reordering
   • System optimisation: balance the performance of the components

Answer: The three pipeline hazards each cost performance in a different way. A data hazard makes a later instruction wait for the result of an earlier one, which is resolved by forwarding, register renaming, or stalling; a control hazard changes the order of execution and forces the pipeline to be flushed, losing several clock cycles, which is resolved by branch prediction, delayed slots, or speculative execution; a structural hazard has several instructions competing for the same hardware resource, which is resolved by adding resources, stalling, or scheduling. In aggregate the actual CPI rises above 1 and the throughput falls short of the ideal, so a pipeline may lose 20-40% of its performance; the remedy is a combination of hardware changes, compiler reordering, and balancing the performance of the components.

Approach: Derive the ideal throughput from the stage count, then the ideal CPI from the same reasoning, and finally compare both with what a real machine achieves once hazards are taken into account.

Steps:

1. The ideal throughput:
   • One instruction is completed per clock cycle
   • Throughput = clock frequency = 2GHz = 2,000 MIPS
2. The ideal CPI:
   • Each instruction needs 1 clock cycle
   • CPI = 1
3. In practice:
   • Affected by pipeline hazards
   • The actual CPI > 1
   • The actual throughput < 2,000 MIPS
4. Performance analysis:
   • In the ideal case the performance is very high
   • In practice the performance is affected by hazards
   • Optimisation is needed to reduce the hazards

Answer: In the ideal case one instruction is completed per clock cycle, so the throughput = clock frequency = 2GHz = 2,000 MIPS, and each instruction needs 1 clock cycle, so CPI = 1. In practice the pipeline hazards raise the actual CPI above 1 and pull the actual throughput below 2,000 MIPS, so the real performance is lower than the ideal and optimisation is needed to reduce the hazards.

Approach: Design in five steps — the stages, the forwarding paths, the conditions that trigger forwarding, the control logic, and the performance tuning — and for the forwarding paths give the exact stage-to-stage connections.

Steps:

1. The pipeline stages:
   • IF: the fetch stage
   • ID: the decode stage
   • EX: the execute stage
   • MEM: the memory access stage
   • WB: the write-back stage
2. The forwarding paths:
   • EX/MEM → EX: forwarding at the execute stage
   • MEM/WB → EX: forwarding at the memory access stage
   • MEM/WB → ID: forwarding at the write-back stage
3. The forwarding conditions:
   • The source register is the same as the destination register
   • The previous instruction writes back to that register
   • The later instruction needs to read that register
4. The control logic:
   • Hazard detection unit
   • Forwarding control unit
   • Pipeline control unit
5. Performance optimisation:
   • Reduces the impact of data hazards
   • Raises the pipeline efficiency
   • Lowers the CPI

Answer: The design uses the classic five stages — IF for the fetch, ID for the decode, EX for the execute, MEM for the memory access, and WB for the write-back — and adds three forwarding paths: EX/MEM → EX for forwarding at the execute stage, MEM/WB → EX for forwarding at the memory access stage, and MEM/WB → ID for forwarding at the write-back stage. Forwarding is triggered when the source register is the same as the destination register, the previous instruction writes back to that register, and the later instruction needs to read it. The control side consists of a hazard detection unit, a forwarding control unit, and a pipeline control unit, which together reduce the impact of data hazards, raise the pipeline efficiency, and lower the CPI.