This is a beta course, so its structure, chapters, and examples may continue to change.
CISC and RISC
1. CISC (Complex Instruction Set Computer)
Basic Concepts
The definition of CISC:
- Complex Instruction Set Computer
- A computer with a complex instruction set
- The instructions are powerful and their formats are varied
The design philosophy:
- Reduce the length of a program by providing complicated instructions
- Raise the code density
- Simplify the design of the compiler
CISC Characteristics
Instruction characteristics:
- Diverse instructions: all kinds of complicated operations are supported
- Variable lengths: the length of an instruction varies
- Powerful functions: a single instruction completes a complicated job
- Rich addressing: many addressing modes are supported
Hardware characteristics:
- Microprogrammed control: a microprogram implements the complicated instructions
- Complicated decoding: a complex instruction decoder is required
- Multi-cycle execution: a complicated instruction needs several cycles
- Complex hardware: the control logic is complex
Software characteristics:
- High code density: the program is short
- Simple compilation: the compiler design is relatively straightforward
- Backwards compatibility: older programs are still supported
- Rich features: it supports high-level language features
Example CISC Instructions
Complicated instructions:
; String copy instructions
MOVSB ; Copy one byte
MOVSW ; Copy one word
MOVSD ; Copy one double word
; Loop instructions
LOOP label ; Loop control
REP MOVSB ; Repeat a string operation
; Complex addressing
MOV AX, [BX+SI+100] ; Base plus index addressingAdvantages:
- High code density: it reduces the space the program occupies
- Powerful functions: it supports complicated operations
- Good compatibility: it supports older programs
Disadvantages:
- Low execution efficiency: complicated instructions execute slowly
- Complex hardware: the control logic is complex
- Hard to pipeline: the instruction lengths are not uniform
2. RISC (Reduced Instruction Set Computer)
Basic Concepts
The definition of RISC:
- Reduced Instruction Set Computer
- A computer with a reduced instruction set
- The instructions are simple and their formats are uniform
The design philosophy:
- Raise the execution efficiency by keeping the instructions simple
- Make pipelining easy to implement
- Optimise the hardware design
RISC Characteristics
Instruction characteristics:
- Simple instructions: every instruction does one thing
- Fixed lengths: the length of an instruction is uniform
- Regular formats: the instruction formats are standardised
- Simple addressing: register addressing is used for the most part
Hardware characteristics:
- Hardwired control: it is implemented with combinational logic
- Simple decoding: instruction decoding is simple and fast
- Single-cycle execution: most instructions complete in a single cycle
- Simple hardware: the control logic is simple
Software characteristics:
- Low code density: the program is longer
- Complicated compilation: the compiler has to do the optimisation
- Register optimisation: register allocation has to be optimised
- Pipeline friendly: it is easy to implement a pipeline
Example RISC Instructions
Simple instructions:
; Load and store instructions
LOAD R1, [R2] ; Load from memory into a register
STORE R1, [R2] ; Store a register into memory
; Arithmetic instructions
ADD R1, R2, R3 ; R1 = R2 + R3
SUB R1, R2, R3 ; R1 = R2 - R3
; Branch instructions
BEQ R1, R2, label ; Branch if equal
BNE R1, R2, label ; Branch if not equalAdvantages:
- High execution efficiency: simple instructions execute quickly
- Simple hardware: the control logic is simple
- Pipeline friendly: the instruction formats are regular
Disadvantages:
- Low code density: the program is longer
- Complicated compilation: the compiler has to optimise
- Simple functions: complicated operations are not supported
3. Comparing CISC and RISC
Comparing the Instruction Characteristics
Instruction complexity:
- CISC: the instructions are complicated and the functions are powerful
- RISC: the instructions are simple and each does one thing
Instruction length:
- CISC: the length varies and the formats are diverse
- RISC: the length is fixed and the formats are uniform
Addressing modes:
- CISC: the addressing modes are rich
- RISC: register addressing is used for the most part
Comparing the Hardware Implementations
Control style:
- CISC: microprogrammed control, which is complex
- RISC: hardwired control, which is simple
Decoding complexity:
- CISC: decoding is complicated and multi-level
- RISC: decoding is simple and single-level
Execution efficiency:
- CISC: multi-cycle execution, which is inefficient
- RISC: single-cycle execution, which is efficient
Comparing the Software Support
Code density:
- CISC: high code density, short programs
- RISC: low code density, long programs
Compilation complexity:
- CISC: compilation is relatively simple
- RISC: compilation requires optimisation
Compatibility:
- CISC: good backwards compatibility
- RISC: relatively poor compatibility
4. The Evolution of Modern Processors
The Convergence Trend
Modern CISC:
- Borrows the design ideas of RISC
- Uses a RISC core internally
- Keeps CISC compatibility on the outside
Modern RISC:
- Adds support for complicated instructions
- Raises the code density
- Optimises the compiler design
Hybrid Architectures
The x86-64 architecture:
- A CISC interface on the outside
- A RISC core on the inside
- Dynamic translation technology
The ARM architecture:
- A reduced instruction set
- An efficient pipeline
- A low-power design
Development Trends
Performance optimisation:
- Raise the degree of instruction-level parallelism
- Optimise the pipeline design
- Strengthen branch prediction
Power control:
- Dynamic frequency scaling
- Multi-core design
- Heterogeneous computing
Feature enhancement:
- Support for vector instructions
- Security instruction extensions
- Support for virtualisation
5. Where Each Architecture Fits
Where CISC Fits
Desktop computing:
- High demands on compatibility
- Code density matters
- The functional requirements are complicated
Server applications:
- Backwards compatibility
- Complicated business logic
- High demands on stability
Embedded systems:
- A rich set of functions
- High development efficiency
- Cost control
Where RISC Fits
Mobile devices:
- Low power requirements
- High performance requirements
- Battery life
High-performance computing:
- Parallel processing
- Pipeline optimisation
- Vector operations
Internet of Things devices:
- Simple control
- Low power consumption
- Cost sensitivity
Exercise 1
What are the main differences between CISC and RISC?
Approach: Work through the five axes on which the two architectures differ — the instructions, the hardware, the software support, the performance characteristics, and the workloads each one suits.
Steps:
- Instruction characteristics:
- CISC: the instructions are complicated and powerful, and their length varies
- RISC: the instructions are simple and each does one thing, and their length is fixed
- Hardware implementation:
- CISC: microprogrammed control, complicated decoding, multi-cycle execution
- RISC: hardwired control, simple decoding, single-cycle execution
- Software support:
- CISC: high code density, simple compilation, good compatibility
- RISC: low code density, complicated compilation, poor compatibility
- Performance characteristics:
- CISC: low execution efficiency, complex hardware, hard to pipeline
- RISC: high execution efficiency, simple hardware, pipeline friendly
- Application scenarios:
- CISC: desktop computing, servers, embedded systems
- RISC: mobile devices, high-performance computing, the Internet of Things
Answer: CISC favours code density and compatibility at the cost of complex decoding and uneven timing, while RISC favours simple, uniform, pipeline-friendly execution at the cost of code length and compiler complexity. The present-day processor designs blend the two, exposing a CISC interface and executing a RISC core.
Exercise 2
How is the effective address of an instruction computed?
Approach: Go through the addressing modes one by one, writing the formula for the effective address in each case and noting whether the value is used directly or has to be fetched first.
Steps:
- Immediate addressing: effective address = the immediate value in the instruction; no computation is needed, the value is used directly.
- Direct addressing: effective address = the address code; the address code is used directly as the address.
- Indirect addressing: effective address = [address code]; the contents of the address code are fetched first and used as the address.
- Register addressing: effective address = the contents of the register; the register value is used directly.
- Register indirect addressing: effective address = [register contents]; the register contents are fetched first and used as the address.
- Base addressing: effective address = base register + displacement; the base register contents are added to the displacement.
- Indexed addressing: effective address = index register + base address; the index register contents are added to the base address.
- Relative addressing: effective address = PC + displacement; the program counter is added to the displacement.
Answer: The effective address is always computed from the instruction’s address code, a register, or the program counter, according to the addressing mode. The modes differ only in where the components come from and in how many memory accesses the computation costs.
| Term | Abbreviation | Explanation |
|---|---|---|
| Complex instruction set computer | CISC | An architecture whose instructions are powerful |
| Reduced instruction set computer | RISC | An architecture whose instructions are simple and efficient |
| Instruction-level parallelism | ILP | The execution of several instructions in parallel |
| Pipeline | - | The technology that overlaps the execution of instructions |
| Superscalar | - | A pipeline that issues more than one instruction per cycle |
| Very long instruction word | VLIW | Multi-issue scheduling driven by the compiler |
| Register window | - | The register management technique of RISC |
| Delay slot | - | The instruction slot after a branch instruction |
| Load/store architecture | - | An architecture in which only memory instructions access memory |
| Fixed-length instruction | - | An instruction whose length is fixed |
| Variable-length instruction | - | An instruction whose length varies |
| Addressing mode | - | The way the address of an operand is found |
| Hardwired control | - | A controller implemented in hardware |
| Microprogrammed control | - | A controller implemented with a microprogram |
| Control store | - | The memory that holds the microprogram |
| Microinstruction | - | The basic unit of a microprogram |
| Microoperation | - | The most basic hardware operation |
| Advanced RISC Machine | ARM | The mainstream RISC architecture |
| Microprocessor without Interlocked Pipeline Stages | MIPS | The classic RISC architecture |
| x86 | - | The mainstream CISC architecture |