This is a beta course, so its structure, chapters, and examples may continue to change.

How a Computer Works and How Its Performance Is Measured

Understanding how a computer works is as important as understanding how a car engine turns over. Only once you know the internal mechanism can you really learn to optimise performance and diagnose problems.

The Stored-Program Principle: Where the Computer Revolution Began

Von Neumann’s Ingenious Innovation

In 1945 the mathematician John von Neumann proposed an idea that looked simple and changed the world:

Both the program instructions and the data are stored in binary form in the same memory, and the computer executes the instructions automatically in the order in which they are stored.

What is revolutionary about this concept is that a program is no longer a piece of hardware circuitry but software that can be stored, modified, and transferred just like data!

What Made It Revolutionary?

Before the stored program:

Computers were special-purpose machines: one machine per task
Changing what the machine did required rewiring it (ENIAC took weeks to rewire)
Programmers were effectively “wire operators”

After the stored program:

A single computer can execute any program
Changing what it does only means loading a different program
The computer became a genuine “general-purpose machine”

The three core ideas of the stored program:

Programs and data are stored together: both exist in memory in binary form
Sequential execution: instructions execute in address order (unless a branch is taken)
Automatic control: the controller fetches, decodes, and executes on its own, with no human intervention

These three points turned the computer from a “calculator” into a “programmable general-purpose machine”!

What a Program Looks Like in Memory

Memory Address	Contents	Description
0x1000	10110001	Instruction: LOAD R1, [0x2000]
0x1004	10110010	Instruction: LOAD R2, [0x2004]
0x1008	00000011	Instruction: ADD R3, R1, R2
0x100C	11000011	Instruction: STORE R3, [0x2008]
…	…	…
0x2000	00000101	Data: 5
0x2004	00000011	Data: 3
0x2008	00000000	Data: destination slot (will hold 8)

Key point: the CPU cannot tell whether a given binary number is an instruction or data; that depends entirely on how it is used!

Why is it said that 'programs and data are essentially the same'? What does this mean in practice?

Why they are essentially the same:

Both are stored in binary form
Both occupy memory space
Both can be read and modified
The CPU cannot distinguish them by form

What it means in practice:

Positive applications:

Compilers: read source code (data) and produce an executable (program)
JIT compilation: compile code (data) into machine code (program) at run time
Dynamic loading: a program loads a plugin while running (data becomes program)
Self-modifying code: a program rewrites its own instructions

Security hazards:

Viruses: disguised as data files, they turn into malicious programs once executed
Buffer overflows: data overwrites program code, and malicious instructions run
Code injection: malicious code is written into a data area and then executed

This is why modern operating systems distinguish “executable” from “non-executable” memory regions!

The Instruction Execution Process: the “Heartbeat” of a Computer

A computer executing a program repeats a cycle, much as a human heart beats over and over.

The Five Stages of the Instruction Cycle

The complete process the CPU goes through to execute one instruction, usually divided into five stages: instruction fetch (IF), instruction decode (ID), execute (EX), memory access (MEM), and write back (WB).

This cycle repeats until the program terminates.

Fetch IF

Decode ID

Execute EX

Memory MEM

Write Back WB

After the write-back stage the cycle loops back to the fetch stage and continues with the next instruction.

Stage 1: Instruction Fetch (IF)

Goal: fetch the next instruction to be executed from memory

Detailed steps:

The program counter (PC) holds the address of the next instruction
The value in the PC is sent onto the address bus
Memory returns the instruction for that address
The instruction travels back to the CPU over the data bus
The instruction is stored in the instruction register (IR)
The PC is incremented by 1 (or by the instruction length), pointing at the next instruction

Time: typically 1-2 clock cycles

Stage 2: Instruction Decode (ID)

Goal: work out what the instruction means and prepare the resources it needs

Detailed steps:

The instruction decoder analyses the operation code in the IR
It determines the instruction class (arithmetic, logic, memory access, branch, and so on)
It identifies where the operands live (register, memory, immediate)
It reads the operands out of the registers
It computes the memory address, if one is needed
It prepares the control signals

Time: typically 1 clock cycle

Stage 3: Execute (EX)

Goal: carry out the operation the instruction specifies

Detailed steps:

Arithmetic instructions: the ALU performs addition, subtraction, multiplication, or division
Logic instructions: the ALU performs AND, OR, NOT, XOR
Shift instructions: the shifter performs a left or right shift
Branch instructions: the target address is computed
Memory access instructions: the memory address is computed

Time: 1 to several clock cycles, depending on the complexity of the operation

Stage 4: Memory Access (MEM)

Goal: access the data memory, if the instruction needs to

Detailed steps:

LOAD instruction: reads data from memory
STORE instruction: writes data to memory
Other instructions: this stage is skipped

Time: 1-2 cycles on a cache hit; 10-100 cycles on a main memory access

Stage 5: Write Back (WB)

Goal: write the result back to its destination

Detailed steps:

The result of the operation is written to the target register
The status flags are updated (zero flag, carry flag, overflow flag, and so on)
The machine is prepared to execute the next instruction

Time: typically 1 clock cycle

A Concrete Example: the ADD Instruction

Instruction: ADD R3, R1, R2 (R3 = R1 + R2)

IF (fetch): the instruction “ADD R3, R1, R2” is fetched from memory address 0x1000, PC: 0x1000 → 0x1004

ID (decode): the operation is ADD, the sources are R1 and R2, the destination is R3; the value of R1 is read (assume 5) and the value of R2 is read (assume 3)

EX (execute): the ALU performs the addition: 5 + 3 = 8

MEM (memory access): this instruction needs no memory access, so the stage is skipped

WB (write back): the result 8 is written to R3, and the status flags are updated (if the result is zero, the zero flag is set)

Total time: 5 clock cycles (without pipelining)

A Concrete Example: the LOAD Instruction

Instruction: LOAD R1, [R2+100] (read the data at memory address R2+100 into R1)

IF (fetch): the instruction “LOAD R1, [R2+100]” is fetched from memory, and the PC is incremented by 1

ID (decode): the operation is LOAD, the source is the memory location [R2+100], the destination is R1; the value of R2 is read (assume 0x2000)

EX (execute): the memory address is computed: 0x2000 + 100 = 0x2064

MEM (memory access): the data is read from memory address 0x2064 (assume 42)

WB (write back): the data 42 is written to R1

Why five stages?

Not three: too coarse, and the pipeline cannot be kept busy
Not seven: too fine-grained, and the control logic becomes unnecessarily complex
Five is just right: it balances pipeline efficiency against control complexity

A modern CPU may actually have 10-20 pipeline stages, but the underlying idea is the same!

Why do different instructions take different amounts of time to execute? What does that mean for performance?

Why the execution times differ:

Memory instructions are slow:
- They have to access memory (the MEM stage)
- On a cache miss they may cost dozens or hundreds of cycles
Complex operations are slow:
- Multiplication is slower than addition (it takes several cycles)
- Division is slower still (it may take dozens of cycles)
- Floating-point operations are usually slower than integer ones
Branches disturb the pipeline:
- A mispredicted branch flushes the pipeline
- That costs several cycles

What this means for performance:

CPI is not a constant:
- Different programs have different CPIs
- Memory-bound programs have a high CPI
- Compute-bound programs can have a much lower one
Directions for optimisation:
- Reduce memory accesses (use registers)
- Avoid complex operations (use a shift where a multiply would do)
- Reduce branches
Compiler optimisations:
- Instruction scheduling: reorder instructions to reduce stalls
- Loop unrolling: reduce the number of branches
- Register allocation: reduce memory accesses

This is why the same algorithm can become several times or even several dozen times faster once it is optimised!

Performance Metrics: How to Measure “Fast” Scientifically

“Is this computer fast?” looks like a simple question, but in reality it is complex. We need several metrics to judge performance in a balanced way.

The Metric System

The metric system:

Category	Metrics
Speed metrics	Clock frequency, CPI, IPC, MIPS
Time metrics	CPU time, response time, throughput
Efficiency metrics	Energy efficiency, performance per dollar, Amdahl’s law

1. Clock Frequency

The frequency of the internal clock signal of the CPU; it says how many times per second the CPU oscillates. The unit is the hertz (Hz).

1 GHz = 10^9 Hz = one billion oscillations per second

\text{Clock Frequency} = \frac{1}{\text{Clock Period}}

For example: if the clock period is 0.2 nanoseconds, the clock frequency is 1 / (0.2 × 10^-9) = 5 GHz

Real examples:

Intel Core i9-13900K: 3.0 GHz base, up to 5.8 GHz
AMD Ryzen 9 7950X: 4.5 GHz base, up to 5.7 GHz
Apple M2: up to 3.5 GHz (but with extremely high energy efficiency)

A higher clock frequency does not mean better performance!

A counter-example:

Intel Pentium 4 (3.8 GHz) < Intel Core 2 Duo (2.4 GHz)
Why? Because the Core 2 Duo’s architecture is more efficient, so it accomplishes more per cycle

The three factors that decide performance:

Clock frequency (how fast)
Architecture (how efficiently)
Number of cores (how much in parallel)

2. CPI (Cycles Per Instruction)

The average number of clock cycles needed to execute one instruction. The smaller the CPI, the more efficient the CPU.

\text{CPI} = \frac{\text{Total Clock Cycles}}{\text{Total Instructions}}

For a mixture of instruction types:

\text{Average CPI} = \sum_{i=1}^{n} (\text{CPI}_i \times \text{Instruction}_i\text{ Share})

Example: suppose a program consists of:

50% of instructions with CPI = 1 (simple arithmetic)
30% of instructions with CPI = 2 (memory accesses)
20% of instructions with CPI = 5 (multiplication)

Average CPI = 0.5×1 + 0.3×2 + 0.2×5 = 0.5 + 0.6 + 1.0 = 2.1

Typical CPI values:

Simple RISC processors: CPI ≈ 1-2
Complex CISC processors: CPI ≈ 2-4
Superscalar processors: CPI < 1 (IPC > 1, several instructions per cycle)

3. CPU Execution Time

This is the most important performance metric of all!

\text{CPU Time} = \text{Instruction Count} \times \text{CPI} \times \text{Clock Period}

Or equivalently:

\text{CPU Time} = \frac{\text{Instruction Count} \times \text{CPI}}{\text{Clock Frequency}}

This is the basic equation of computer performance!

To improve performance (that is, to reduce CPU time), you can:

Reduce the instruction count: optimise the algorithm, let the compiler optimise
Lower the CPI: improve the CPU architecture, reduce memory accesses
Raise the clock frequency: improve the manufacturing process, cool the machine better

The three constrain one another, so they have to be balanced!

A worked example:

Program A:

Instruction count: 1,000,000
CPI: 2
Clock frequency: 2 GHz

CPU time = (1,000,000 × 2) / (2 × 10^9) = 0.001 s = 1 ms

Program B (after optimisation):

Instruction count: 800,000 (20% fewer)
CPI: 2.5 (slightly higher)
Clock frequency: 2 GHz

CPU time = (800,000 × 2.5) / (2 × 10^9) = 0.001 s = 1 ms

Conclusion: although the CPI went up, the instruction count fell by exactly as much, so the total time is unchanged!

4. MIPS (Million Instructions Per Second)

\text{MIPS} = \frac{\text{Instruction Count}}{\text{Execution Time} \times 10^6}

Or equivalently:

\text{MIPS} = \frac{\text{Clock Frequency}}{\text{CPI} \times 10^6}

Example:

Clock frequency: 3 GHz
CPI: 2

MIPS = 3000 / 2 = 1500 MIPS

Why can MIPS mislead you?

Instructions differ in complexity:
- A simple addition and a complex division both count as one instruction
- A high MIPS figure does not mean the real work is done faster
MIPS differs from program to program:
- The same CPU running different programs can produce very different MIPS figures
The compiler matters:
- After optimisation the instruction count falls and the MIPS figure drops, yet the program is genuinely faster!

5. Throughput vs. Response Time

The number of tasks completed per unit of time. It measures the overall processing capacity of a system.

Units: tasks/second, transactions/second, requests/second

The time taken to complete a single task. It measures how quickly one individual task is handled.

Units: seconds, milliseconds, microseconds

The relationship:

Throughput ≈ 1 / average response time
But the two are not identical (queueing, concurrency, and other factors intervene)

An example: a restaurant

High throughput:

A fast-food restaurant serves 100 customers an hour
But each customer may have to queue for 5 minutes

Low response time:

A fine dining restaurant serves a guest the moment they arrive
But it can only serve 20 customers an hour

The trade-off in computing:

Servers: chase high throughput (handle more requests)
Personal computers: chase low response time (react to the user quickly)

6. Amdahl’s Law: the Limit of Parallel Speedup

It describes the theoretical ceiling on the speedup a program can obtain from parallelisation. It was proposed by Gene Amdahl in 1967.

The core idea: the speedup of a program is limited by the part of it that cannot be parallelised.

\text{Speedup} = \frac{1}{(1-P) + \frac{P}{N}}

where:

P = the fraction of the program that can be parallelised (between 0 and 1)
N = the number of processors
(1-P) = the fraction that is serial

Example 1: 90% of the program can be parallelised

With 4 processors:

\text{Speedup} = \frac{1}{0.1 + \frac{0.9}{4}} = \frac{1}{0.1 + 0.225} = \frac{1}{0.325} \approx 3.08

With an infinite number of processors:

\text{Speedup} = \frac{1}{0.1 + 0} = 10

Conclusion: even with infinitely many processors, the program can at best become 10 times faster!

Example 2: 50% of the program can be parallelised

With an infinite number of processors:

\text{Speedup} = \frac{1}{0.5} = 2

Conclusion: at best 2 times faster!

Why can adding processors never give you an unlimited speedup?

The harsh reality Amdahl’s law reveals:

The serial part is the bottleneck:
- No matter how many processors there are, the serial part still executes one step at a time
- It is like a motorway that is widened but still has a single toll booth
The real speedup is even lower:
- Communication overhead: processors need time to talk to each other
- Load imbalance: some processors are busy while others idle
- Synchronisation overhead: waiting for the other processors to finish
Optimisation strategy:
- Optimise the serial part first: reduce (1-P)
- Then parallelise: increase P
- Only then add processors: increase N

Real examples:

Video rendering: 95% parallelisable, so it scales well
Database transactions: 30% parallelisable, so the speedup is limited
Compiling code: 70% parallelisable, so the speedup is moderate

This is why not every program suits a multi-core processor!

A Real CPU Performance Comparison

Intel Core i9-13900K vs AMD Ryzen 9 7950X

Metric	Intel i9-13900K	AMD Ryzen 9 7950X
Cores	24 cores (8P+16E)	16 cores
Threads	32	32
Base frequency	3.0 GHz	4.5 GHz
Peak frequency	5.8 GHz	5.7 GHz
Cache	L2 32MB + L3 36MB	L2 16MB + L3 64MB
TDP	125W (base) / 253W (peak)	170W
Process	Intel 7 (10nm)	TSMC 5nm

Performance comparison (Cinebench R23):

Single core: i9-13900K ≈ 2200 points, 7950X ≈ 2000 points
Multi core: i9-13900K ≈ 40000 points, 7950X ≈ 38000 points

Conclusion: the performance is close and each has its own strengths

Intel: slightly stronger single-core performance, better gaming performance
AMD: better energy efficiency, stronger sustained multi-core performance

Exercises

Basic Exercises (1-4)

Exercise 1

Briefly describe the five stages of instruction execution and state the main task of each stage.

Reference Answer

Instruction CycleIF ID EX MEM WBFetch Decode Execute

Approach: Walk through the cycle in order, naming the five stages and the concrete work each one performs, then state the property that ties them together.

Steps:

Fetch (IF - Instruction Fetch): the instruction is read from memory at the address held by the PC; it is stored in the IR; the PC is incremented so that it points at the next instruction.
Decode (ID - Instruction Decode): the operation code is analysed; the instruction class and the location of the operands are determined; the operands are read out of the registers; the control signals are prepared.
Execute (EX - Execute): the ALU performs the arithmetic or logic operation; for a memory access instruction the memory address is computed; for a branch instruction the target address is computed.
Memory access (MEM - Memory Access): a LOAD instruction reads data from memory and a STORE instruction writes data to memory; every other instruction skips this stage.
Write back (WB - Write Back): the result of the operation is written to the target register; the status flags (zero flag, carry flag, and so on) are updated; the machine is prepared for the next instruction.

Answer: The five stages are instruction fetch, instruction decode, execute, memory access, and write back. Together they form one complete instruction cycle, which repeats over and over until the program finishes.

Exercise 2

A certain CPU has a clock period of 0.25 nanoseconds. What is its clock frequency in GHz?

Reference Answer

Clock FrequencyClock PeriodCPU Time

Approach: Apply the relation between clock frequency and clock period, substitute the given period, and convert the result into GHz.

Steps:

The formula is: clock frequency = 1 / clock period
Substitute the period of 0.25 ns and convert nanoseconds to seconds.

Answer:

\text{Clock Frequency} = \frac{1}{0.25 \times 10^{-9}} = \frac{1}{0.25} \times 10^9 = 4 \times 10^9 \text{ Hz} = 4 \text{ GHz}

The clock frequency is 4 GHz.

Exercise 3

A program contains the following instructions:

40% of instructions with CPI = 1
30% of instructions with CPI = 2
30% of instructions with CPI = 4

Find the average CPI of the program.

Reference Answer

CPIAverage CPIWeighted Average

Approach: Use the weighted-average formula for a mixture of instruction types, weighting each CPI by the share of instructions that has it.

Steps:

The weighted average formula is:

\text{Average CPI} = \sum (\text{CPI}_i \times \text{Share}_i)

Substitute the three instruction classes:

\text{Average CPI} = 1 \times 0.4 + 2 \times 0.3 + 4 \times 0.3

Add up the contributions:

= 0.4 + 0.6 + 1.2 = 2.2

Answer: The average CPI is 2.2. This means that on average each instruction takes 2.2 clock cycles to execute.

Exercise 4

A program contains 1,000,000 instructions, has an average CPI of 2.5, and runs on a CPU with a 2 GHz clock frequency. Find the CPU execution time.

Reference Answer

CPU TimeCPIInstruction Count

Approach: Use the CPU time formula with the instruction count, the CPI, and the clock frequency, then verify the result by counting cycles directly.

Steps:

The CPU time formula is:

\text{CPU Time} = \frac{\text{Instruction Count} \times \text{CPI}}{\text{Clock Frequency}}

Substitute the given values:

\text{CPU Time} = \frac{1,000,000 \times 2.5}{2 \times 10^9}

Simplify:

= \frac{2,500,000}{2,000,000,000} = 0.00125 \text{ s} = 1.25 \text{ ms}

Answer: The CPU execution time is 1.25 ms.

Verification:

Total cycles = 1,000,000 × 2.5 = 2,500,000 cycles
Time per cycle = 1 / (2×10^9) = 0.5 ns
Total time = 2,500,000 × 0.5 ns = 1.25 ms ✓

Intermediate Exercises (5-6)

Exercise 5

Compare the performance of two CPUs:

CPU A:

Clock frequency: 3 GHz
CPI: 2
The program needs 10,000,000 instructions

CPU B:

Clock frequency: 4 GHz
CPI: 3
The same program needs 8,000,000 instructions (better compiler optimisation)

Which CPU runs the program faster, and by how much?

Reference Answer

CPU TimeSpeedupPerformance Comparison

Approach: Compute the CPU time of each processor from the instruction count, the CPI, and the clock frequency, then take the ratio to obtain the speedup.

Steps:

The execution time of CPU A:

\text{Time}_A = \frac{10,000,000 \times 2}{3 \times 10^9} = \frac{20,000,000}{3,000,000,000} = 0.00667 \text{ s} \approx 6.67 \text{ ms}

The execution time of CPU B:

\text{Time}_B = \frac{8,000,000 \times 3}{4 \times 10^9} = \frac{24,000,000}{4,000,000,000} = 0.006 \text{ s} = 6 \text{ ms}

The speedup:

\text{Speedup} = \frac{\text{Time}_A}{\text{Time}_B} = \frac{6.67}{6} \approx 1.11

Answer: CPU B is faster, by about 11% (or 0.67 ms).

Analysis:

CPU B has the higher CPI (that is, lower efficiency), but it also has the higher clock frequency and the smaller instruction count
Compiler optimisation removed 20% of the instructions, and that turned out to be the decisive factor
This shows that performance is not only about hardware; software optimisation matters just as much!

Exercise 6

60% of a program’s code can be parallelised. Using Amdahl’s law, what is the theoretical speedup with 4 processors? And with 16 processors?

Reference Answer

Amdahl LawSpeedupParallelism

Approach: Apply Amdahl’s law for each processor count, then compute the limit as the number of processors tends to infinity.

Steps:

The Amdahl’s law formula is:

\text{Speedup} = \frac{1}{(1-P) + \frac{P}{N}}

Here P = 0.6 (the parallelisable part) and 1-P = 0.4 (the serial part).
With 4 processors:

\text{Speedup}_4 = \frac{1}{0.4 + \frac{0.6}{4}} = \frac{1}{0.4 + 0.15} = \frac{1}{0.55} \approx 1.82

With 16 processors:

\text{Speedup}_{16} = \frac{1}{0.4 + \frac{0.6}{16}} = \frac{1}{0.4 + 0.0375} = \frac{1}{0.4375} \approx 2.29

The theoretical limit, with an infinite number of processors:

\text{Speedup}_{\infty} = \frac{1}{0.4} = 2.5

Answer:

4 processors: a speedup of about 1.82
16 processors: a speedup of about 2.29
The theoretical limit: 2.5

Analysis:

Going from 4 cores to 16 cores buys only 0.47 of extra speedup
The 40% serial part caps the speedup
Even with infinitely many processors the program can at best become 2.5 times faster
This is why the serial part has to be optimised first!

Advanced Exercises (7-8)

Exercise 7

A program has the following original performance:

Execution time: 10 seconds
Of which memory operations take 60% (6 seconds)
And computation takes 40% (4 seconds)

Two optimisation options are available:

Option A: optimise the memory operations so that their time falls by 50%
Option B: optimise the computation so that its time falls by 70%

Which option gives the better result, and why?

Reference Answer

Amdahl LawSpeedupBottleneck

Approach: Compute the new total time and the speedup for each option, then re-derive the same result through Amdahl’s law to show which part dominates.

Steps:

Option A (optimise the memory operations):
- Memory time: 6 seconds × 50% = 3 seconds (3 seconds saved)
- Computation time: 4 seconds (unchanged)
- Total time: 3 + 4 = 7 seconds
- Speedup: 10 / 7 ≈ 1.43
Option B (optimise the computation):
- Memory time: 6 seconds (unchanged)
- Computation time: 4 seconds × 30% = 1.2 seconds (2.8 seconds saved)
- Total time: 6 + 1.2 = 7.2 seconds
- Speedup: 10 / 7.2 ≈ 1.39
The same result through Amdahl’s law:
- Option A:

\text{Speedup} = \frac{1}{0.4 + \frac{0.6}{2}} = \frac{1}{0.7} \approx 1.43

Option B:

\text{Speedup} = \frac{1}{0.6 + \frac{0.4}{3.33}} = \frac{1}{0.72} \approx 1.39

Answer: Option A gives the better result (0.2 seconds faster).

Deeper analysis: This is Amdahl’s law in practice. Optimising the part that carries the larger share — the 60% spent on memory access — wins even though the percentage improvement is smaller (50% against 70%), because the base is larger. The general rule is make the common case fast!

Exercise 8

You have to buy a server for a company and there are two options:

Server A:

CPU: Intel Xeon, 3.5 GHz, 16 cores
Memory: 64GB DDR4-3200
Price: $3000
Strong single-core performance, suited to single-threaded work

Server B:

CPU: AMD EPYC, 2.8 GHz, 32 cores
Memory: 128GB DDR4-3200
Price: $4000
Strong multi-core performance, suited to parallel work

The company’s main workload is:

70% web serving (high concurrency, highly parallelisable)
30% database queries (partly parallelisable)

Which one would you choose? Please explain your reasoning.

Reference Answer

Server SelectionAmdahl LawWorkload

Approach: Characterise the workload, weigh the strengths of each server against it, estimate the parallel performance of each, and only then apply the cost consideration.

Steps:

Workload characteristics: web serving (70%) is highly concurrent and can make full use of many cores; database queries (30%) are only partly parallelisable and still benefit from single-core performance.
Server A’s strengths: strong single-core performance at 3.5 GHz; $1000 cheaper; suited to single-threaded work.
Server B’s strengths: twice the core count (32 against 16); twice the memory (128GB against 64GB); suited to high-concurrency scenarios.
Performance estimate for web serving (assuming it parallelises fully):
- Server A: 16 cores × 3.5 GHz = 56 GHz·cores
- Server B: 32 cores × 2.8 GHz = 89.6 GHz·cores
- Server B is about 60% faster here
Performance estimate for the database queries (assuming 50% parallelisable): by Amdahl’s law the multi-core advantage is discounted, but Server B still has the edge.
Future growth: more cores and more memory are worth more as the business grows.

Answer: Choose Server B. It matches the workload, because 70% of the traffic is highly concurrent web serving that uses all 32 cores; its 128GB of memory serves both the web tier and the database tier; it leaves more headroom for growth; and even though it costs $1000 more, the performance gain exceeds 33%. If the budget were tight, if the work were predominantly single-threaded, or if the highest possible single-core performance were the priority, Server A would be the better choice. There is no absolute “best” here — only the better fit for a stated requirement.

Basic Components of a Computer System

Comprehensive Exercises

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How a Computer Works and How Its Performance Is Measured

The Stored-Program Principle: Where the Computer Revolution Began

Von Neumann’s Ingenious Innovation

What Made It Revolutionary?

What a Program Looks Like in Memory

The Instruction Execution Process: the “Heartbeat” of a Computer

The Five Stages of the Instruction Cycle

Stage 1: Instruction Fetch (IF)

Stage 2: Instruction Decode (ID)

Stage 3: Execute (EX)

Stage 4: Memory Access (MEM)

Stage 5: Write Back (WB)

A Concrete Example: the ADD Instruction

A Concrete Example: the LOAD Instruction

Performance Metrics: How to Measure “Fast” Scientifically

The Metric System

1. Clock Frequency

2. CPI (Cycles Per Instruction)

3. CPU Execution Time

4. MIPS (Million Instructions Per Second)

5. Throughput vs. Response Time

6. Amdahl’s Law: the Limit of Parallel Speedup

A Real CPU Performance Comparison

Intel Core i9-13900K vs AMD Ryzen 9 7950X

Exercises

Basic Exercises (1-4)

Exercise 1

Exercise 2

Exercise 3

Exercise 4

Intermediate Exercises (5-6)

Exercise 5

Exercise 6

Advanced Exercises (7-8)

Exercise 7

Exercise 8